Host bus adapters are well known in the art, e.g., for establishing and maintaining an interface between a very fast bus, e.g., a fibre channel and a host computer and/or local network of host computers. They function to perform many tasks, e.g., reassembling and checking the correctness of packets of communicated information received over the input channel, e.g., a fibre channel and, e.g., serializing the data for transmission to the host computer, e.g., over a serial bus to the serial bus port of the host computer, and the like. As the communication channels are becoming even more capable of increasing the bit transmission rate (“BTR”) there is a need for a new architecture for a host bus adapter, particularly one implemented on a microchip.